1. Field of the Invention
The embodiments described herein are directed to fabrication of integrated circuit devices, and more particularly to methods for forming a shallow trench isolation (STI) region in a semiconductor substrate during fabrication of an integrated circuit device.
2. Background of the Invention
As integrated circuits gets smaller and smaller, the need to provide isolation between devices comprising the integrated circuit has increased. The need for isolation between devices comprising today's integrated circuits is also affected by the increasing density of devices within each circuit. Today's integrated circuits comprised millions of transistors packed into ever smaller spaces. Without isolation between various devices comprising an integrated circuit, the performance of these integrated circuits would be affected by leakage current, and other parasitic effects that exists between the various transistors and devices.
In the fabrication of high-density circuits, shallow trench isolation (STI) structures have become prevalent, and are used almost as exclusively to provide isolation for conventional integrated circuit devices. STI is a method for forming isolation regions between devices on a semiconductor substrate used to form an integrated circuit. STI typically comprises anisotropically etching a semiconductor substrate to form a trench, and then depositing oxide material to fill the trench. Since the STI structure can be scaled, problems that affected previous isolation techniques can be avoided, making STI an ideal method for isolating, e.g. even submicron complimentary MOS devices.
As device geometries continue to shrink, and device densities continue to increase, problems with conventional STI processes have been exposed. For example, before the oxide material is deposited to fill the trench, a liner oxide layer can be formed so as to line the inside of trench. The oxide material deposited into the trench can then be formed into a compact insulation layer by heating the oxide material to a high temperature. But this process can result in stress on the active regions surrounding the trench. Accordingly, the compaction process is typically carried out in a nitrogen filled atmosphere rather than an oxygen filled atmosphere. By performing the step in a nitrogen filled atmosphere, oxidation of the trench sidewalls is prevented, which can reduce the accumulation of stress.
Unfortunately, using a nitrogen filled atmosphere results in an insulation layer inside the trench that is less compact. When the pad oxide layers defining the active areas around the trench are removed, e.g., using a hydrofluoric acid solution, the etching rate of the insulation layer inside the trench can be higher than that of the pad oxide layer. As a result, the combination of etching of the pad oxide layer with isotropic etching of the insulation layer within the trench can produce stress on the various layers at the top and bottom corners of the trench. This stress can produce a phenomenon known as dislocation, or dislocation effect. The dislocation effect can cause a lowering of the threshold voltage of devices formed in the active area as well as the formation of parasitic MOSFETs around the corners of the device formed in the active region. These parasitic MOSFETs can produce large leakage currents between devices.
In order to reduce the dislocation effect, a silicon nitride (SiN) layer is often formed over the oxide liner within the trench. The SiN layer prevents oxidation and allows the insulation layer formed within the trench to be formed in an oxygen filled atmosphere, which produces a more compact insulation layer within the trench. Unfortunately, the SiN layer can contribute to a thinning of a gate oxide layer formed in an active area adjacent to the trench. The thinning can reduce the available active area, because the thin gate oxide layer can result in undesirable parasitic and leakage currents when devices formed in the active region impinge, or are formed too close to the thinned gate oxide layer.
FIGS. 1A-1F are schematic, cross sectional diagrams illustrating the progression of manufacturing steps for a conventional method for fabricating an STI structure using an SiN layer to reduce dislocation. First, as shown in FIG. 1A, a pad oxide layer 102 is formed over a silicon substrate 100 using a thermal oxidation method. Pad oxide layer 102 protects silicon substrate 100 against damages in subsequent processing operations. Thereafter, a silicon nitride mask layer 104 is formed over pad oxide layer 102.
Next, as shown in FIG. 1B, conventional photolithography techniques are used to form trench 108. Hence, a patterned mask layer 104a and pad oxide layer 102a as well as a trench 108 are formed above substrate 100.
Next, as shown in FIG. 1C, a liner oxide layer 110 is formed on the exposed substrate surface of trench 108. As can be seen, liner oxide layer 110 extends from the bottom of trench 108 to the top corners 120 where it contacts pad oxide layer 102a. After liner oxide layer 110 is formed in trench 108, a silicon nitride film 112 can then be formed over liner oxide layer 110 within trench 108. Thereafter, insulating material is deposited into trench 108 and over silicon nitride layer 104a and silicon nitride film 112 to form an insulation layer 116. Insulation layer 116 can, for example, be a silicon oxide layer. Subsequently, substrate 100 is heated to a high temperature so that the silicon oxide material is allowed to densify into a compact insulation layer 116.
As illustrated in FIG. 1D, a CMP process can be carried out to remove portions of insulation layer 116 using silicon nitride layer 104a as a polishing stop layer, while retaining a portion of insulating layer of 116a within trench 108.
As shown in FIG. 1E, a hot phosphoric acid can then be applied to remove silicon nitride layer 104a, thereby exposing pad oxide layer 102a. A hydrofluoric (HF) acid solution can then be applied to remove pad oxide layer 102a. The remaining insulation layer 116a and liner oxide layer 110 within the trench 108 of the substrate 100 forms a complete device isolation region 118.
The surface of silicon substrate 100 can then be thermally oxidized to form a SAC oxide layer 128 over substrate 100. Impurity ions of the desired conductivity type can be implanted into the surface layer of silicon substrate 100 via the SAC oxide layer 128, and activated to form the desired conductivity type in the surface layer of silicon substrate 100. SAC oxide layer 128 can then be removed using a diluted hydrofluoric acid solution as illustrated in FIG. 1F.
Due to the presence of silicon nitride film 112, insulating layer 116a can be densified using an oxygen filled atmosphere. Unfortunately, the presence of silicon nitride film 112 can prevent removal off insulation layer 110 adjacent to the top corners 126 of trench 108, which can lead to subsequent thinning of the gate oxide layer as illustrated in FIG. 2.
FIG. 2 is a diagram illustrating a TEM image of an STI region 200 formed in a silicon substrate 202. As can be seen, STI structure 200 comprises a trench 212 filled with an insulating layer 210. Trench 212 is also lined with the liner oxide layer 206 and the silicon nitride film 208. As can be seen, gate oxide layer 216 has been thinned at the upper corner of trench 212 in region 204.
Thinning occurs because while silicon nitride film 112 is used to cap liner oxide layer 110 in order to decrease HDP thermal expansion and reduce isolation, it also caps the top corners of liner oxide layer 110. This affects the rounding of the top corners of liner oxide layer 110 and leads to the thinning illustrated in the TEM image of FIG. 2.